The present disclosure relates to a semiconductor memory device, and more particularly to a semiconductor memory device having bit lines hierarchized through transistors.
Memories included in recent systems on chip (SOCs) tend to become larger in capacity and higher in speed. With a larger memory capacity, the number of memory cells connected to a bit line is increasing. This increases the load capacitance of the bit line, and thus hinders achievement of higher speed. To decrease the bit-line load capacitance, a hierarchical bit line technique is known where a bit line is divided into a plurality of banks, memory cells in each bank are connected to a local bit line, and the local bit line is connected to a global bit line through a transistor (see U.S. Pat. No. 7,480,189 (Patent Document 1), for example).
In a semiconductor memory device of Patent Document 1, as shown in FIG. 3 of this document, bit lines are hierarchically constituted by a pair of first and second local bit lines to which a plurality of memory cells are connected and a pair of first and second global bit lines for transferring input/output data to/from the first and second local bit lines.
Sense amplifiers are connected to the first and second global bit lines for execution of read and write operations. The first local bit line and the first global bit line are connected to each other through a first transfer transistor, and the second local bit line and the second global bit line are connected to each other through a second transfer transistor.
The semiconductor memory device of Patent Document 1 further includes first and second write transistors. The first write transistor has a source to which a write control signal is supplied, a drain connected to the first local bit line, and a gate connected to the second global bit line. The second write transistor has a source to which the write control signal is supplied, a drain connected to the second local bit line, and a gate connected to the first global bit line.
[Write Operation]
The write operation of the semiconductor memory device of Patent Document 1 will be described. In the write operation, write data is passed to the first and second global bit lines through the sense amplifiers. This changes the voltage level of either the first or second global bit line from high to low. In response to the voltage change of the global bit line, either the first or second write transistor is switched from on to off. Thereafter, the write control signal changes from high to low, allowing the voltage level of either the first or second local bit line to change from high to low by the first or second write transistor whichever is on. At about the timing when the write data appears on the first and second local bit lines, a word line control signal changes from low to high, allowing the data to be written into a memory cell according to the voltage levels of the first and second local bit lines.
[Read Operation]
The read operation of the semiconductor memory device of Patent Document 1 will be described. In the read operation, the word line control signal changes from low to high. This causes data to be read from a memory cell, changing the voltage level of either the first or second local bit line from high to low. Thereafter, the first and second transfer transistors are switched from off to on, allowing the voltage levels of the first and second local bit lines to be passed to the first and second global bit lines, respectively. When the potential difference between the first and second global bit lines reaches a given value, the sense amplifiers start up. In this way, data stored in the memory cell is read.